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e product preview december 1996 order number: 290599-003 n smartvoltage technology ? smart 5 flash: 5v reads, 5v or 12v writes ? increased programming throughput at 12v v pp n very high-performance read ? 2-, 4-mbit: 60 ns access time ? 8-mbit: 70 ns access time n x8/x16-configurable input/output bus n low power consumption ? max 60 ma read current at 5v ? auto power savings: <1 ma typical standby current n optimized array blocking architecture ? 16-kb protected boot block ? two 8-kb parameter blocks ? 96-kb and 128-kb main blocks ? top or bottom boot locations n extended temperature operation ? C40c to +85c n industry-standard packaging ? 44-lead psop, 48-lead tsop n extended block erase cycling ? 100,000 cycles at commercial temp ? 10,000 cycles at extended temp n hardware data protection feature ? absolute hardware-protection for boot block ? write lockout during power transitions n automated word/byte program and block erase ? command user interface ? status registers ? erase suspend capability n sram-compatible write interface n reset/deep power-down input ? provides low-power mode and reset for boot operations n pinout compatible 2, 4, and 8 mbit n etox? flash technology ? 0.6 m etox iv initial production ? 0.4 m etox v later production intels word-wide smart 5 boot block flash memory family provides 2-, 4-, and 8-mbit memories featuring high-density, low-cost, nonvolatile, read/write storage solutions for a wide range of applications. their asymmetrically-blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for embedded code execution applications, such as networking infrastructure and office automation. based on intels boot block architecture, the word-wide smart 5 boot block memory family enables quick and easy upgrades for designs that demand state-of-the-art technology. this family of products comes in industry-standard packages: the 48-lead tsop, ideal for board-constrained applications, and the rugged, easy to handle 44-lead psop. smart 5 boot block flash memory family 2, 4, 8 mbit 28f200b5, 28f400b5, 28F800B5
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f200b5, 28f400b5, 28F800B5 may contain design defects or errors known are errata. current characterized errata are available on request. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 copyright ? intel corporation, 1996 cg-041493
e smart 5 boot block memory family 3 product preview contents page page 1.0 introduction ............................................. 5 1.1 new features in the smart 5 memory products ..................................................... 5 1.2 product overview ........................................ 5 2.0 product description.............................. 6 2.1 pin descriptions........................................... 6 2.2 pinouts......................................................... 8 2.3 memory blocking organization .................. 10 2.3.1 boot block........................................... 10 2.3.2 parameter blocks................................ 10 2.3.3 main blocks......................................... 10 3.0 principles of operation ..................... 13 3.1 bus operations .......................................... 13 3.1.1 read ................................................... 13 3.1.2 output disable .................................... 14 3.1.3 standby............................................... 14 3.1.4 word/byte configuration ..................... 14 3.1.5 deep power-down/reset.................... 14 3.1.6 write ................................................... 14 3.2 modes of operation ................................... 16 3.2.1 read array.......................................... 16 3.2.2 read identifier..................................... 16 3.2.3 read status register .......................... 16 3.2.4 word/byte program............................. 17 3.2.5 block erase......................................... 17 3.3 boot block locking .................................... 24 3.3.1 v pp = v il for complete protection ....... 24 3.3.2 wp# = v il for boot block locking ....... 24 3.3.3 rp# = v hh or wp# = v ih for boot block unlocking ........................................... 24 3.3.4 note for 8-mbit 44-psop package...... 24 4.0 design considerations........................24 4.1 power consumption...................................24 4.1.1 active power .......................................24 4.1.2 automatic power savings (aps) .........24 4.1.3 standby power ....................................25 4.1.4 deep power-down mode.....................25 4.2 power-up/down operation.........................25 4.2.1 rp# connected to system reset .......25 4.3 board design .............................................25 4.3.1 power supply decoupling....................25 4.3.2 v pp trace on printed circuit boards ...25 5.0 specifications.........................................26 5.1 absolute maximum ratings........................26 5.2 test conditions ..........................................26 5.3 operating conditions .................................27 5.4 reset operations .......................................27 5.6 electrical specifications .............................28 dc characteristics table ...........................28 ac characteristics: read operations table........................................................30 ac characteristics: write operations table........................................................32 erase and program timings ......................34 appendix a: ordering information .................35 appendix b: write state machine: current- next state chart..........................................36 appendix c: product block diagram .............37 appendix d: additional information...............38
smart 5 boot block memory family e 4 product preview revision history number description -001 original version -002 minor changes throughout document. section 3.1.5 and figure 13 redone to clarify program/erase operation abort. information added to table 2, figure 1, and section 3.3 to clarify wp# on 8-mbit, 44-psop. read and write waveforms changed to numbered format. typical numbers removed from dc characteristics and erase/program timings. -003 minor text changes throughout document. figure 1, 44-psop pinout: mistake on pin 3 on 2-mbit pinout corrected from a 17 to nc. specs t ehqz and t ghqz improved. explanations of program/erase abort commands reworked in table 6, command codes.
e smart 5 boot block memory family 5 product preview 1.0 introduction this datasheet contains specifications for 2-, 4-, and 8-mbit smart 5 boot block flash memories. section 1 provides a feature overview. sections 2, 3, and 4 describe the product and functionality. section 5 details the electrical and timing specifications for both commercial and extended temperature operation. 1.1 new features in the smart 5 memory products the smart 5 boot block flash memory family offers identical features with the bv/cv/be/ce smartvoltage products, except the smart 5 boot block -b5 parts only support 5v v cc read voltage. the following differences distinguish the smart 5 boot block products from their predecessors: a delay is required if the part is reset during an in-progress program or erase operation. on the fly word-byte mode switching is no longer supported. word-byte mode must be configured at power-up and remain stable during operation. write operations are no longer specified as we#- or ce#-controlled in favor of a simpler unified write method, which is compatible with either of the old methods. 1.2 product overview the word-wide smart 5 boot block memory family provides pinout-compatible flash memories at the 2-, 4- and 8-mbit densities. the 28f200b5, 28f400b5, and 28F800B5 can be configured to operate either in 16-bit or 8-bit bus mode, with the data divided into individually erasable blocks. table 1. smart 5 boot block family: feature summary feature 28f200b5 28f400b5 28F800B5 reference v cc read voltage 5v 5%, 5v 10% table 10 v pp prog/erase voltage 5v 10% or 12v 5%, auto-detected table 10 bus-width 8- or 16-bit configurable table 2 speed (ns) commercial 60, 80 60, 80 70, 90 table 14 extended 80 80 90 table 14 memory arrangement x8: 256k x 8 x16: 128k x 16 x8: 512k x 8 x16: 256k x 16 x8: 1m x 8 x16: 512k x 16 blocking (top or bottom boot locations available) 1 x 16k boot block 2 x 8k parameter 1 x 96k main block 1 x 128k main block 1 x 16k boot block 2 x 8k parameter 1 x 96k main block 3 x 128k main block 1 x 16k boot block 2 x 8k parameter 1 x 96k main block 7 x 128k main block sect. 2.3, fig. 3-6 locking boot block lockable using wp# and/or rp# all others protectable using v pp switch sect. 3.3 operating temperature commercial: 0c C +70 c extended: -40c C +85 c table 10 erase cycling 100,000 cycles at commercial temperature 10,000 cycles at extended temperature packages 44-psop, 48-tsop figs. 1-2
smart 5 boot block memory family e 6 product preview smartvoltage technology enables fast factory programming and low-power designs. specifically designed for 5v systems, smart 5 com ponents support read operations at 5v v cc and internally configure to program/erase at 5v or 12v. the 12v v pp option renders the fastest program and erase performance which will increase your factory throughput. with the 5v v pp option, v cc and v pp can be tied together for a simple 5v design. in addition, the dedicated v pp pin gives complete data protection when v pp v pplk . the memory array is asymmetrically divided into blocks in an asymmetrical architecture to accommodate microprocessors that boot from the top (denoted by -t suffix) or the bottom ( -b suffix) of the memory map. the blocks incl ude a hardware-lockable boot block (16,384 bytes), two parameter blocks (8, 192 bytes each) and main blocks ( one block of 98,304 bytes and additional block(s) of 131,072 bytes). see figures 3 C6 for memory maps. each block can be independently erased and programmed 100,000 times at commercial temperature or 10,000 times at extended temperature. unlike erase operations, which erase all locations within a block simultaneously, each byte or word in the flash memory can be programmed independently of other memory locations. the hardware-lockable boot block provides complete code security for the kernel code required for system initialization. locking and unlocking of the boot block is controlled by wp# and/or rp# (see section 3.3 for details). the system processor interfaces to the flash device through a command user interface (cui), using valid command sequences to initiate device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for program and erase operations. the status register (sr) indicates the status of the wsm and whether it successfully completed the desired program or erase operation. the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i ccr current is 1 ma. when ce# and rp# pins are at v cc , the component enters a cmos standby mode. driving rp# to gnd enables a deep power-down mode which significantly reduces power consumption, provides write protection, resets the device, and clears the status register. a reset time (t phqv ) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (t phel ) from rp#-high until writes to the cui are recognized. see section 4.2. the deep power-down mode can also be used as a device reset, allowing the flash to be reset along with the rest of the system. for example, w hen the flash memory powers-up, it automatically defaults to the read array mode, but during a warm system reset, where power continues uninterrupted to the system com ponents, the flash memory could remain in a non-read mode, such as erase. consequently, the system reset si gnal should be tied to rp# to reset the memory to normal read mode upon activation of the reset signal. this also provides protection against unwanted command writes due to invalid system bus c onditions during system reset or power-up/down sequences. these devices are configurable at power-up for either byte-wide or word-wide input/output using the byte# pin. please see table 2 for a detailed description of byte# operations, especially the usage of the dq 15 /a C1 pin. these smart 5 memory products are available in the 44-lead psop (plastic small outline package), which is rom/eprom-compatible, and the 48-lead tsop (thin small outline package, 1.2 mm thick) as shown in figure 1, and 2, respectively. 2.0 product description this section describes the pinout and block architecture of the device family. 2.1 pin descriptions the pin descriptions table details the usage of each of the device pins.
e smart 5 boot block memory family 7 product preview table 2. pin descriptions symbol type name and function a 0 Ca 18 input address inputs for memory addresses. addresses are internally latched during a write cycle. 28f200: a[0-16], 28f400: a[0-17], 28f800: a[0-18] a 9 input address input: when a 9 is at v hh the signature mode is accessed. during this mode, a 0 decodes between the manufacturer and device ids. when byte# is at a logic low, only the lower byte of the signatures are read. dq 15 /a C1 is a dont care in the signature mode when byte# is low. dq 0 Cdq 7 input/ output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. inputs commands to the command user interface when ce# and we# are active. data is internally latched during the write cycle. outputs array, intelligent identifier and status register data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled. dq 8 Cdq 15 input/ output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. data is internally latched during the write cycle. outputs array data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled as in the byte-wide mode (byte# = 0). in the byte-wide mode dq 15 /a C1 becomes the lowest order address for data output on dq 0 Cdq 7 . ce# input chip enable: activates the devices control logic, input buffers, decoders and sense amplifiers. ce# is active low. ce# high de-selects the memory device and reduces power consumption to standby levels. if ce# and rp# are high, but not at a cmos high level, the standby current will increase due to current flow through the ce# and rp# input stages. oe# input output enable: enables the devices outputs through the data buffers during a read cycle. oe# is active low. we# input write enable: controls writes to the command register and array blocks. we# is active low. addresses and data are latched on the rising edge of the we# pulse. rp# input reset/deep power-down: uses three voltage levels (v il , v ih , and v hh ) to control two different functions: reset/deep power-down mode and boot block unlocking. it is backwards-compatible with the bx/bl/bv products. when rp# is at logic low, the device is in reset/deep power-down mode , which puts the outputs at high-z, resets the write state machine, and draws minimum current. when rp# is at logic high, the device is in standard operation . when rp# transitions from logic-low to logic-high, the device defaults to the read array mode. when rp# is at v hh , the boot block is unlocked and can be programmed or erased. this overrides any control from the wp# input.
smart 5 boot block memory family e 8 product preview table 2. pin descriptions (continued) symbol type name and function wp# input write protect: provides a method for unlocking the boot block with a logic level signal in a system without a 12v supply. when wp# is at logic low, the boot block is locked , preventing program and erase operations to the boot block. if a program or erase operation is attempted on the boot block when wp# is low, the corresponding status bit (bit 4 for program, bit 5 for erase) will be set in the status register to indicate the operation failed. when wp# is at logic high, the boot block is unlocked and can be programmed or erased. note: this feature is overridden and the boot block unlocked when rp# is at v hh . this pin can not be left floating. because the 8-mbit 44-psop package does not have enough pins, it does not include this pin and thus 12v on rp# is required to unlock the boot block. see section 3.3 for details on write protection. byte# input byte# enable: configures whether the device operates in byte-wide mode (x8) or word-wide mode (x16). this pin must be set at power-up or return from deep power-down and not changed during device operation. byte# pin must be controlled at cmos levels to meet the cmos current specification in standby mode. when byte# is at logic low, the byte-wide mode is enabled , where data is read and programmed on dq 0 Cdq 7 and dq 15 /a C1 becomes the lowest order address that decodes between the upper and lower byte. dq 8 Cdq 14 are tri-stated during the byte-wide mode. when byte# is at logic high, the word-wide mode is enabled , where data is read and programmed on dq 0 Cdq 15 . v cc device power supply: 5.0v 10% v pp program/erase power supply: for erasing memory array blocks or programming data in each block, a voltage either of 5v 10% or 12v 5% must be applied to this pin. when v pp < v ppl k all blocks are locked and protected against program and erase commands. gnd ground: for all internal circuitry. nc no connect: pin may be driven or left floating. 2.2 pinouts intels smart 5 boot block architecture provides upgrade paths in each package pinout up to the 8-mbit density. the 44-lead psop pinout follows the industry-standard rom/eprom pinout, as shown in figure 1. designs with space concerns should consider the 48-lead pinout shown in figure 2. pinouts for the corresponding 2-, 4- and 8-mbit components are provided on the same diagram for convenient reference. 2-mbit pinouts are given on the chip illustration in the center, with 4-mbit and 8-mbit pinouts going outward from the center.
e smart 5 boot block memory family 9 product preview pa28f200 boot block 44-lead psop 0.525" x 1.110" top view gnd we# rp# byte# a 8 a 9 a 11 a 12 a 13 a 14 a 16 dq 7 dq 14 dq 6 dq 13 dq 12 dq 4 v cc dq 5 a 10 a 15 32 31 30 29 28 27 26 25 24 23 33 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 28f400 28f400 dq 15 -1 /a ce# gnd oe# v pp 28f800 28f800 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 a 18 ce# gnd oe# v pp a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 wp# ce# gnd oe# v pp nc a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 wp# gnd we# rp# byte# a 8 a 9 a 11 a 12 a 13 a 14 a 16 dq 7 dq 14 dq 6 dq 13 dq 12 dq 4 v cc dq 5 a 10 a 15 dq 15 -1 /a gnd we# rp# byte# a 8 a 9 a 11 a 12 a 13 a 14 a 16 dq 7 dq 14 dq 6 dq 13 dq 12 dq 4 v cc dq 5 a 10 a 15 dq 15 -1 /a 0599-01 note: pin 2 is wp# on 2- and 4-mbit devices but a 18 on the 8-mbit because no other pins were available for the high order address. thus, the 8-mbit in 44-psop cannot unlock the boot block without rp# = v hh . see section 3.3 for details. to allow upgrades to 8-mbit from 2/4-mbit in this package design pin 2 to control wp# at the 2/4-mbit level and a 18 at the 8-mbit density. figure 1. 44-lead psop pinout diagram 28f200 boot block 48-lead tsop 12 mm x 20 mm top view 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 25 26 27 28 29 30 31 32 ce# oe# gnd a 0 v cc gnd byte# a 16 dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 dq 3 ce# oe# gnd a 0 v cc gnd byte# a 16 dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 dq 3 ce# oe# gnd a 0 v cc gnd byte# a 16 dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 dq 3 28f400 28f800 28f400 28f800 rp# we# nc nc nc wp# a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 v pp a 17 a 6 a 7 a 4 a 5 a 3 a 2 rp# we# nc nc nc wp# a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 v pp a 6 a 7 a 4 a 5 a 3 a 2 rp# we# nc nc nc wp# a 18 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 v pp a 17 a 6 a 7 a 4 a 5 a 3 a 2 nc nc nc 1 a 1 a 1 a 0599-02 figure 2. 48-lead tsop pinout diagram
smart 5 boot block memory family e 10 product preview 2.3 memory blocking organization the boot block product family features an asymmetrically-blocked architecture providing system memory integration. each erase block can be erased independently of the others up to 100,000 times for commercial temperature or up to 10,000 times for extended temperature. the block sizes have been chosen to optimize their functionality for common applications of nonvolatile storage. the combination of block sizes in the boot block architecture allow the integration of several memories into a single chip. for the address locations of the blocks, see the memory maps in figures 3, 4, 5 and 6. 2.3.1 one 16-kb boot block the boot block is intended to replace a dedicated boot prom in a microprocessor or microcontroller- based system. the 16-kbyte (16, 384 bytes) boot block is located at either the top (denoted by -t suffix) or the bottom (-b suffix) of the address map to accommodate different microprocessor protocols for boot code location. this boot block features hardware controllable write-protection to protect the crucial microprocessor boot code from accidental modification. the protection of the boot block is controlled using a combination of the v pp , rp#, and wp# pins, as is detailed in section 3.3. 2.3.2 two 8-kb parameter blocks each boot block component contains two parameter blocks of 8 kbytes (8, 192 bytes) each to facilitate storage of frequently updated small parameters that would normally require an eeprom. by using software techniques, the byte-rewrite functionality of eeproms can be emulated. these techniques are detailed in intels application note, ap-604 using intels boot block flash memory parameter blocks to replace eeprom . the parameter blocks are not write-protectable. 2.3.3 main blocks - one 96-kb + additional 128-kb blocks after the allocation of address space to the boot and parameter blo cks, the remai nder is divided into main blocks for data or c ode storage. each device contains one 96-kbyte (98,304 byte) block and additional 128-kbyte (131,072 byte) blo cks. the 2-mbit has one 128-kb block; the 4-mbit, three; and the 8-mbit, seven.
e smart 5 boot block memory family 11 product preview 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 00000h 0ffffh 10000h 1ffffh 20000h 2ffffh 30000h 3ffffh 40000h 4ffffh 50000h 5ffffh 60000h 6ffffh 70000h 7bfffh 7c000h 7cfffh 7d000h 7dfffh 7e000h 7ffffh 28f800-t 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 00000h 0ffffh 10000h 1ffffh 20000h 2ffffh 30000h 3bfffh 3c000h 3cfffh 3d000h 3dfffh 3e000h 3ffffh 28f400-t 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 00000h 0ffffh 10000h 1bfffh 1c000h 1cfffh 1d000h 1dfffh 1e000h 1ffffh 28f200-t 0599-03 note: word addresses shown. figure 3. word-wide x16-mode memory maps (top boot) 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 7ffffh 70000h 6ffffh 60000h 5ffffh 50000h 4ffffh 40000h 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh 04000h 03fffh 03000h 02fffh 02000h 01fffh 00000h 28f800-b 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh 04000h 03fffh 03000h 02fffh 02000h 01fffh 00000h 28f400-b 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 1ffffh 10000h 0ffffh 04000h 03fffh 03000h 02fffh 02000h 01fffh 00000h 28f200-b 0599-04 note: word addresses shown. figure 4. word-wide x16-mode memory maps (bottom boot)
smart 5 boot block memory family e 12 product preview 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 00000h 1ffffh 20000h 3ffffh 40000h 5ffffh 60000h 7ffffh 80000h 9ffffh a0000h bffffh c0000h dffffh e0000h f7fffh f8000h f9fffh fa000h fbfffh fc000h fffffh 28f800-t 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 00000h 1ffffh 20000h 3ffffh 40000h 5ffffh 60000h 77fffh 78000h 79fffh 7a000h 7bfffh 7c000h 7ffffh 28f400-t 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 00000h 1ffffh 20000h 37fffh 38000h 39fffh 3a000h 3bfffh 3c000h 3ffffh 28f200-t byte-mode addresses 0599-05 note: in x8 operation, the least significant system address should be connected to a -1 . figure 5. byte-wide x8-mode memory maps (top boot) 128-kbyte main block 28f200-b 8-kbyte parameter block 16-kbyte boot block 28f400-b 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block fffffh e0000h dffffh c0000h bffffh a0000h 9ffffh 80000h 7ffffh 60000h 5ffffh 40000h 3ffffh 20000h 1ffffh 08000h 07fffh 06000h 05fffh 04000h 03fffh 00000h 28f800-b 7ffffh 60000h 5ffffh 40000h 3ffffh 20000h 1ffffh 08000h 07fffh 06000h 05fffh 04000h 03fffh 00000h 3ffffh 20000h 1ffffh 08000h 07fffh 06000h 05fffh 04000h 03fffh 00000h byte-mode addresses 0599-06 note: in x8 operation, the least significant system address should be connected to a -1 . figure 6. byte-wide x8-mode memory maps (bottom boot)
e smart 5 boot block memory family 13 product preview 3.0 principles of operation the system processor accesses the smart 5 boot block memories through the command user interface (cui), which accepts commands written with standard microprocessor write timings and ttl-level control inputs. the flash can be switched into each of its read and write modes through commands issued to the cui. the flash memory has three read modes and two write modes. the read modes are read array, read identifier, and read status. the write modes are program and block erase. an additional mode, erase suspend to read, is available only during suspended block erasures. a comprehensive chart showing the state transitions is in appendix b. after initial device power-up or return from deep power-down mode, the device defaults to read array mode. in this mode, manipulation of the memory control pins allows array read, standby, and output disable operations. the other read modes, read identifier and read status register, can be reached by issuing the appropriate command to the cui. array data, identifier codes and status register results can be accessed using these commands independently from the v pp voltage. read identifier mode can also be accessed by prom programming equipment by raising a 9 to high voltage (v id ). cui commands sequences also control the write functions of the flash memory, program and erase. issuing program or erase command sequences internally latches addresses and data and initiates write state machine (wsm) operations to execute the requested write function. the wsm internally regulates the program and erase algorithms, including pulse repetition, internal verification, and margining of data, freeing the host processor from these tasks and allowing precise control for high reliability. to execute program or erase commands, v pp must be at valid write voltage (5v or 12v). while the wsm is executing a program operation, the device defaults to the read status register mode and all commands are ignored. thus during the programming process, only status register data can be accessed from the device. while the wsm is executing a erase operation, the device also defaults to the read status register mode but one additional command is available, erase suspend to read, which will suspend the erase operation and allow reading of array data. the suspended erase operation can be completed by issuing the erase resume command. after the program or erase operation has completed, the device remains in read status register mode. from this mode any of the other read or write modes can be reached with the appropriate command. for example, to read data, issue the read array command. additional program or erase commands can also be issued from this state. during program or erase operations, the array data is not available for reading or code execution, except during an erase suspend. consequently, the software that initiates and polls progress of program and erase operations must be copied to and executed from system ram during flash memory update. after successful completion, reads are again possible via the read array command. each of the device modes will be discussed in detail in the following sections. 3.1 bus operations the local cpu reads and writes flash memory in- system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. four control pins dictate the data flow in and out of the component: ce#, oe#, we#, and rp#. these bus operations are summarized in table 3 and 4. 3.1.1 read the flash memory has three read modes available, read array, read identifier, and read status. these read modes are accessible independent of the v pp voltage. rp# can be at either v ih or v hh . the appropriate read-mode command must be issued to the cui to enter the corresponding mode. upon initial device power-up or after exit from deep power-down mode, the device automatically defaults to read array mode. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control, and, when active, enables the selected memory device. oe# is the data output (dq 0 Cdq 15 ) control and when active drives the selected memory data onto the i/o bus. in read modes, we# must be at v ih and rp# must be at v ih or v hh . figure 14 illustrates a read cycle.
smart 5 boot block memory family e 14 product preview 3.1.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0 Cdq 15 are placed in a high-impedance state. 3.1.3 standby deselecting the device by bringing ce# to a logic- high level (v ih ) places the device in standby mode which substantially reduces device power consumption. in standby, outputs dq 0 Cdq 15 are placed in a high-impedance state independent of oe#. if deselected during program or erase operation, the device continues functioning and consuming active power until the operation completes. 3.1.4 word/byte configuration the device can be configured for either an 8-bit or 16-bit bus width by setting the byte# pin before power-up. when byte# is set to logic low, the byte-wide mode is enabled, where data is read and programmed on dq 0 Cdq 7 and dq 15 /a C1 becomes the lowest order address that decodes between the upper and lower byte. dq 8 Cdq 14 are tri-stated during the byte-wide mode. when byte# is at logic high, the word-wide mode is enabled, and data is read and programmed on dq 0 Cdq 15 . 3.1.5 deep power-down/reset rp# at v il initiates the deep power-down mode, also referred to as reset mode. from read mode, rp# going low for time t plph deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. after return from power-down, a time t phqv is required until the initial memory access outputs are valid. a delay (t phwl or t phel ) is required after return from power-down before a write can be initiated. after this wake-up interval, normal operation is restored. the cui resets to read array mode, and the status register is set to 80h. this case is shown in figure 13a. if rp# is taken low for time t plph during a program or erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. the abort process goes through the following sequence: when rp# goes low, the device shuts down the operation in progress, a process which takes time t plrh to complete. after this time t plrh , the part will either reset to read array mode (if rp# has gone high during t plrh , figure 13b) or enter deep power-down mode (if rp# is still logic low after t plrh , figure 13c). in both cases, after returning from an aborted operation, the relevant time t phqv or t phwl /t phel must be waited before a read or write operation is initiated, as discussed in the previous paragraph. however, in this case, these delays are referenced to the end of t plrh rather than when rp# goes high. as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, processor expects to read from the flash memory. automated flash memories provide status information when read during program or block erase operations. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. intels flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. 3.1.6 write the cui does not occupy an addressable memory location. instead, commands are written into the cui using standard microprocessor write timings when we# and ce# are low, oe# = v ih , and the proper address and data (command) are presented. the address and data for a command are latched on the rising edge of we# or ce#, whichever goes high first. figure 15 illustrates a write operation.
e smart 5 boot block memory family 15 product preview table 3. bus operations for word-wide mode (byte# = v ih ) mode notes rp# ce# oe# we# a 9 a 0 v pp dq 0 C15 read 1,2,3 v ih v il v il v ih xxx d out output disable v ih v il v ih v ih x x x high z standby v ih v ih xxxxx high z deep power-down 9 v il xxxxxx high z intelligent identifier (mfr.) 4v ih v il v il v ih v id v il x 0089 h intelligent identifier (device) 4,5 v ih v il v il v ih v id v ih x see table 5 write 6,7,8 v ih v il v ih v il xxx d in table 4. bus operations for byte-wide mode (byte# = v il ) mode notes rp# ce# oe# we# a 9 a 0 a C1 v pp dq 0C7 dq 8C14 read 1,2,3 v ih v il v il v ih xxxxd out high z output disable v ih v il v ih v ih xxxx high z high z standby v ih v ih xxxxxx high z high z deep power- down 9v il xxxxxxx high z high z intelligent identifier (mfr.) 4v ih v il v il v ih v id v il x x 89h high z intelligent identifier (device) 4,5 v ih v il v il v ih v id v ih x x see table 5 high z write 6,7,8 v ih v il v ih v il xxxxd in high z notes: 1. refer to dc characteristics. 2. x can be v il , v ih for control pins and addresses, v pplk or v pph for v pp . 3. see dc characteristics for v pplk , v pph1 , v pph2 , v hh , v id voltages. 4. manufacturer and device codes may also be accessed via a cui write sequence, a 0 selects, all other addresses = x. 5. see table 5 for device ids. 6. refer to table 7 for valid d in during a write operation. 7. command writes for block erase or program are only executed when v pp = v pph1 or v pph2 . 8. to program or erase the boot block, hold rp# at v hh or wp# at v ih . see section 3.3. 9. rp# must be at gnd 0.2v to meet the maximum deep power-down current specified.
smart 5 boot block memory family e 16 product preview 3.2 modes of operation the flash memory has three read modes and two write modes. the read modes are read array, read identifier, and read status. the write modes are program and block erase. an additional mode, erase suspend to read, is available only during suspended block erasures. these modes are reached using the commands summarized in table 6. a comprehensive chart showing the state transitions is in appendix b. 3.2.1 read array after initial device power-up or return from deep power-down mode, the device defaults to read array mode. this mode can also be entered by writing the read array command (ffh). the device remains in this mode until another command is written. data is read by presenting the address of the read location in conjunction with a read bus operation. once the wsm has started a program or block erase operation, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend command. the read array command functions independently of the v pp voltage and rp# can be v ih or v hh . during system design, consideration s hould be taken to ensure address and control inputs meet required input slew rates of <10 ns as defined in figures 10 and 11. 3.2.2 read identifier to read the manufacturer and device codes, the device must be in intelligent identifier read mode, which can be reached using two methods: by writing the intelligent identifier command (90h) or by taking the a 9 pin to v id . once in intelligent identifier read mode, a 0 = 0 outputs the manufacturers identification code and a 0 = 1 outputs the device code. in byte-wide mode, only the lower byte of the above signatures is read (dq 15 /a C1 is a dont care in this mode). see table 5 for product signatures. to return to read array mode, write a read array command (ffh). table 5 . word-mode intelligent identifier codes product mfr. id device id -t top boot -b bottom boot 28f200 0089 h 2274 h 2275 h 28f400 0089 h 4470 h 4471 h 28f800 0089 h 889c h 889d h note: in byte-mode, the upper byte will be tri-stated. 3.2.3 read status register the device status register indicates when a program or erase operation is complete, and the success or failure of that operation. the status register is output when the device is read in read status register mode, which can be entered by issuing the read status (70h) command to the cui. this mode is automatically entered when a program or erase operation is initiated, and the device remains in this mode after the operation has completed. the status register bit codes are defined in table 8 the status register bits are output on dq 0 Cdq 7 , in both byte-wide (x8) or word-wide (x16) mode. in the word-wide mode, the upper byte, dq 8 Cdq 15 , outputs 00h during a read status command. in the byte-wide mode, dq 8 Cdq 14 are tri-stated and dq 15 /a C1 retains the low order address function. note that the contents of the status register are latched on the falling edge of oe# or ce#, whichever occurs last in the read cycle. this prevents possible bus errors which might occur if status register contents change while being read. ce# or oe# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. to return to reading from the array, issue a read array (ffh) command. 3.2.3.1 clearing the status register status register bits sr.5, sr.4, and sr.3 are set to 1s when appropriate by the wsm but can only be reset by the clear status register command. these bits indicate various failure conditions (see table 8). by requiring system software to reset these bits, several operations (such as cumulatively
e smart 5 boot block memory family 17 product preview erasing multiple blocks or programming several bytes in sequence) may be performed before polling the status register to determine if an error occurred during the series. issue the clear status register command (50h) to clear the status register. it functions independently of the applied v pp voltage and rp# can be v ih or v hh . this command is not functional during block erase suspend modes. resetting the part with rp# also clears the status register. 3.2.4 word/byte program word or byte program operations are executed by a two-cycle comm and sequence. program setup (40h) is issued, followed by a second write that specifies the address and data (latched on the rising edge of we# or ce#, whichever comes first). the wsm then takes over, controlling the program and program verify algorithms internally. while the wsm is working, the device automatically enters read status register mode and remains there after the word/byte program is complete. (see figure 7). the completion of the program event is indicated on status register bit sr.7. when a word/byte program is complete, check status register bit sr.4 for an error flag ( 1). the cause of a failure may be found on sr.3, which indicates 1 if v pp was out of program/erase voltage range (v pph1 or v pph2 ). the status register should be cleared before the next operation. the internal wsm verify only detects errors for 1s that do not successfully write to 0s. since the device remains in status register read mode after programming is completed, a command must be issued to switch to another mode before beginning a different operation. 3.2.5 block erase a block erase changes all block data to 1s (ffffh) and is initiated by a two- cycle comm and. an erase setup command (20h) is issued first, followed by an erase confirm command (d0h) along with an address within the target block. the address will be latched at the rising edge of we# or ce#, whichever comes first. internally, the wsm will program all bits in the block to 0, verify all bits are adequately programmed to 0, erase all bits to 1, and verify that all bits in the block are sufficiently erased. after block erase command sequence is issued, the device automatically enters read status register mode and outputs status register data when read (see figure 8). the completion of the erase event is indicated on status register bit sr.7. when an erase is complete, check status register bit sr.5 for an error flag (1). the cause of a failure may be found on sr.3, which indicates 1 if v pp was out of program/erase voltage range (v pph1 or v pph2 ). if an erase setup (20h) command is issued but not followed by an erase confirm (d0h) command, then both the program status (sr.4) and the erase status (sr.5) will be set to 1. the status register should be cleared before the next operation. since the device remains in status register read mode after erasing is completed, a command must be issued to switch to another mode before beginning a different operation. 3.2.5.1 erase suspend/resume the erase suspend command (b0h) interrupts an erase operation in order to read data in another block of memory. while the erase is in progress, issuing the erase suspend command requests that the wsm suspend the erase algorithm after a certain latency period. the device outputs status register data when read after the erase suspend command is issued. status register bits sr.7 and sr.6 indicate when the block erase operation has been suspended (both will be set to 1). at this point, a read array command (ffh) can be written to read from blo cks other t han that which is suspended. the only other valid commands at this time are erase resume (d0h) or read status register. during erase suspend mode, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. v pp must remain at v pph1 or v pph2 (the same v pp level used for block erase) while erase is suspended. rp# must also remain at v ih or v hh (the same rp# level used for block erase). to resume the erase operation, enable the chip by taking ce# to v il , then issue the erase resume command, which continues the erase sequence to completion. as with the end of a standard erase operation, the status register must be read, cleared, and the next instruction issued in order to continue.
smart 5 boot block memory family e 18 product preview table 6. command codes and descriptions code device mode description 00 invalid/ reserved unassigned commands that should not be used. intel reserves the right to redefine these codes for future functions. ff read array places the device in read array mode, so that array data will be output on the data pins. 40 program set-up sets the cui into a state such that the next write will load the address and data registers. the next write after the program set-up command will latch addresses and data on the rising edge and begin the program algorithm. the device then defaults to the read status mode, where the device outputs status register data when oe# is enabled. to read the array, issue a read array command. to cancel a program operation after issuing a program set-up command, write all 1s (ffh for x8, ffffh for x16) to the cui. this will return to read status register mode after a standard program time without modifying array contents. if a program operation has already been initiated to the wsm this command can not cancel that operation in progress. 10 alternate prog set-up (see 40h/program set-up) 20 erase set-up prepares the cui for the erase confirm command. if the next command is not an erase confirm command, then the cui will set both the program status (sr.4) and erase status (sr.5) bits of the status register to a 1, place the device into the read status register state, and wait for another command without modifying array contents. this can be used to cancel an erase operation after the erase setup command has been issued. if an operation has already been initiated to the wsm this can not cancel that operation in progress. d0 erase resume/ erase confirm if the previous command was an erase set-up command, then the cui will latch address and data, and begin erasing the block indicated on the address pins. during erase, the device will respond only to the read status register and erase suspend commands and will output status register data when oe# is toggled low. status register data is updated by toggling either oe# or ce# low. b0 erase suspend valid only while an erase operation is in progress and will be ignored in any other circumstance. issuing this command will begin to suspend erase operation. the status register will indicate when the device reaches erase suspend mode. in this mode, the cui will respond only to the read array, read status register, and erase resume commands and the wsm will also set the wsm status bit to a 1 (ready). the wsm will continue to idle in the suspend state, regardless of the state of all input control pins except rp#, which will immediately shut down the wsm and the remainder of the chip, if it is made active. during a suspend operation, the data and address latches will remain closed, but the address pads are able to drive the address into the read path. see section 3.2.5.1. 70 read status register puts the device into the read status register mode, so that reading the device outputs status register data, regardless of the address presented to the device. the device automatically enters this mode after program or erase has completed. this is one of the two commands that is executable while the wsm is operating. see section 3.2.3.
e smart 5 boot block memory family 19 product preview table 6. command codes and descriptions (continued) code device mode description 50 clear status register the wsm can only set the program status and erase status bits in the status register to 1; it cannot clear them to 0. the status register operates in this fashion for two reasons. the first is to give the host cpu the flexibility to read the status bits at any time. second, when programming a string of bytes, a single status register query after programming the string may be more efficient, since it will return the accumulated error status of the entire string. see section 3.2.3.1. 90 intelligent identifier puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes. (a 0 = 0 for manufacturer, a 0 = 1 for device, all other address inputs are ignored). see section 3.2.2. table 7. command bus definitions first bus cycle second bus cycle command note oper addr data oper addr data read array write x ffh intelligent identifier 2,4 write x 90h read ia iid read status register 3 write x 70h read x srd clear status register 3 write x 50h word/byte program 6,7 write pa 40h/10h write pa pd block erase/confirm 5 write ba 20h write ba d0h erase suspend write x b0h erase resume write x d0h address data ba = block address srd = status register data ia = identifier address iid = identifier data pa = program address pd = program data x = dont care notes: 1. bus operations are defined in tables 3 and 4. 2. ia = identifier address: a 0 = 0 for manufacturer code, a 0 = 1 for device code. 3. srd - data read from status register. 4. iid = intelligent identifier data. following the intelligent identifier command, two read operations access manufacturer and device codes. 5. ba = address within the block being erased. 6. pa = address to be programmed. pd = data to be programmed at location pa. 7. either 40h or 10h commands is valid. 8. when writing commands to the device, the upper data bus [dq 8 Cdq 15 ] = x which is either v il or v ih , to minimize current draw.
smart 5 boot block memory family e 20 product preview table 8. status register bit definition wsms ess es dws vpps r r r 76543210 notes: sr.7 write state machine status 1 = ready (wsms) 0 = busy check wsm bit first to determine word/byte program or block erase completion, before checking program or erase status bits. sr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to 1. ess bit remains set to 1 until an erase resume command is issued. sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase when this bit is set to 1, one of the following has occurred: 1. v pp out of range. 2. wsm has applied the max number of erase pulses to the block and is still unable to verify successful block erasure. 3. erase setup command was followed by a command other than erase confirm. sr.4 = program status (dws) 1 = error in byte/word program 0 = successful byte/word program when this bit is set to 1, one of the following has occurred: 1. v pp out of range. 2. wsm has applied the max number of program pulses and is still unable to verify a successful program. 3. erase setup command was followed by a command other than erase confirm. sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok the v pp status bit does not provide continuous indication of v pp level. the wsm interrogates v pp level only after the program or erase command sequences have been entered, and informs the system if v pp is out of range. the v pp status bit is not guaranteed to report accurate feedback between v pplk and v pph . sr.2-sr.0 = reserved for future enhancements (r) these bits are reserved for future use and should be masked out when polling the status register.
e smart 5 boot block memory family 21 product preview sr.7 = 1 ? no yes start write 40h, word/byte address write word/byte data/address full status check if desired word/byte program complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v pp range error bus operation command comments standby standby check sr.3 1 = v pp low detect sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.4 is only cleared by the clear status register command, in cases where multiple bytes are programmed before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. bus operation command comments write write setup program data = data to program addr = location to program read data = 40h addr = word/byte to program check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent word/byte program operations. sr full status check can be done after each word/byte program operation, or after a sequence of word/byte programs. write ffh after the last program operation to reset device to read array mode. standby sr.3 = sr.4 = word/byte program error word/byte program successful check sr.4 1 = word byte program error program status register data toggle ce# or oe# to update srd. 0599-07 figure 7. automated word/byte program flowchart
smart 5 boot block memory family e 22 product preview sr.7 = 0 1 start write 20h, block address write d0h and block address full status check if desired block erase complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v range error pp suspend erase suspend erase loop yes no 1 0 command sequence error sr.3 = sr.5 = sr.4,5 = block erase error bus operation command comments standby check sr.4,5 both 1 = command sequence error standby check sr.3 1 = v low detect sr.3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.5 is only cleared by the clear status register command, in cases where multiple blocks are erase before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1 = block erase error standby bus operation command comments write write erase setup read data = 20h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent block erasures. full status check can be done after each block erase, or after a sequence of block erasures. write ffh after the last operation to reset device to read array mode. status register data toggle ce# or oe# to update status register standby erase confirm data = d0h addr = within block to be erased block erase successful pp 0599-08 figure 8. automated block erase flowchart
e smart 5 boot block memory family 23 product preview sr.7 = 0 1 start write b0h read status register write d0h erase resumed bus operation command comments write erase suspend read data = b0h addr = x check sr.7 1 = wsm ready 0 = wsm busy status register data toggle ce# or oe# to update srd. addr = x standby csr.6 = write ffh read array data done reading erase completed write ffh read array data yes no 0 1 check sr.6 1 = erase suspended 0 = erase completed standby data = ffh addr = x write read array data from block other than the one being erased. read data = d0h addr = x write read array erase resume 0599-09 figure 9. erase suspend/resume flowchart
smart 5 boot block memory family e 24 product preview 3.3 boot block locking the boot block family architecture features a hardware-lockable boot block so that the kernel code for the system can be kept secure while the parameter and main blo cks are programmed and erased independently as necessary. only the boot block can be locked independently from the other blocks. 3.3.1 v pp = v il for complete protection for complete write protection of all blocks in the device, the v pp voltage can be held low. when v pp is below v pplk , any program or erase operation will result in a error in the status register. 3.3.2 wp# = v il for boot block locking when wp# = v il , the boot block is locked and any program or erase operation to the boot block will result in an error in the status register. all other blocks remain unlocked in this c ondition and can be programmed or erased normally. note that this feature is overridden and the boot block unlocked when rp# = v hh . 3.3.3 rp# = v hh or wp# = v ih for boot block unlocking two methods can be used to unlock the boot block: 1. wp# = v ih 2. rp# = v hh if both or either of these two conditions are met, the boot block will be unlocked and can be programmed or erased. the truth table, table 9, clearly defines the write protection methods. 3.3.4 note for 8-mbit 44-psop package the 8-mbit in the 44-psop package does not have a wp# because no other pins were available for the 8-mbit upgrade address. thus, in this density- package combination only, v hh (12v) on rp# is required to unlock the boot block and unlocking with a logic-level signal is not possible. if this unlocking functionality is required, and 12v is not available in- system, please consider using the 48-tsop package, which has a wp# pin and can be unlocked with a logic-level signal. all other density- package combinations have wp# pins. table 9. write protection truth table v pp rp# wp# write protection provided v il x x all blocks locked 3 v pplk v il x all blocks locked (reset) 3 v pplk v hh x all blocks unlocked 3 v pplk v ih v il boot block locked 3 v pplk v ih v ih all blocks unlocked 4.0 design considerations the following section discusses recommended design considerations which can improve the robustness of system designs using flash memory. 4.1 power consumption intel flash components contain features designed to reduce power requirements. the following sections will detail how to take advantage of these features. 4.1.1 active power asserting ce# to a logic-low level and rp# to a logic-high level places the device in the active mode. refer to the dc characteristics table for i ccr current values. 4.1.2 automatic power savings (aps) automatic power savings (aps) provides low- power operation in active mode. power reduction control (prc) circuitry allows the device to put itself into a low current state when not being accessed. after data is read from the memory array, prc logic controls the devices power consumption by entering the aps mode where typical i cc current is less than 1 ma. the device stays in this static state with outputs valid until a new location is read.
e smart 5 boot block memory family 25 product preview 4.1.3 standby power when ce# is at a logic-high level (v ih ), and the device is not programming or erasing, the memory enters in standby mode, which disables much of the devices circuitry and substantially reduces power consumption. outputs (dq 0 Cdq 15 or dq 0 Cdq 7 ) are placed in a high-impedance state independent of the status of the oe# signal. when ce# is at logic- high level during program or erase operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. 4.1.4 deep power-down mode the smart 5 boot block family supports a low typical i ccd in deep power-down mode, which turns off all circuits to save power. this mode is activated by the rp# pin when it is at a logic-low (gnd 0.2v). note: byte# pin must be at cmos levels to meet the i ccd specification. during read modes, the rp# pin going low de- selects the memory and places the output drivers in a high impedance state. recovery from the deep power-down state, requires a minimum access time of t phqv . rp# transitions to v il , or turning power off to the device will clear the status register. during an program or erase operation, rp# going low for time t plph will abort the operation, but the locations memory contents will no longer valid and additional timing must be met. see section 3.1.5 and 6.1 for additional information. 4.2 power-up/down operation the device protects against accidental block erasure or programming during power transitions. power supply sequencing is not required, so either v pp or v cc can power-up first. the cui defaults to the read mode after power-up, but the system must drop ce# low or present an address to receive valid data at the outputs. a system desi gner must guard against spurious writes when v cc voltages are above v lko and v pp is active. since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. additionally, alteration of memory can only occur after successful completion of a two-step command sequences. the device is also disabled until rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (rp# connected to system powergood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 4.2.1 rp# connected to system reset using rp# properly during system reset is important with automated program/erase devices because the system expects to r ead from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization would not occur because the flash memory may in a mode other than read array. intels flash memories allow proper cpu initialization following a system reset by c onnecting the rp# pin to the same reset# signal that resets the system cpu. 4.3 board design 4.3.1 power supply decoupling flash memorys switching characteristics require careful decoupling methods. system designers should consider three supply current issues: standby current levels (i ccs ), active current levels (i ccr ), and transient peaks produced by falling and rising edges of ce#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between v cc and gnd, and between v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 4.3.2 v pp trace on printed circuit boards in-system updates to the flash memory requires special consideration of the v pp power supply trace by the printed circuit board designer. since the v pp pin supplies the current for programming and erasing, it should have similar trace widths and layout considerations as given to the v cc power supply trace. adequate v pp supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
smart 5 boot block memory family e 26 product preview 5.0 specifications 5.1 absolute maximum ratings* commercial operating temperature during read/erase/program ........ 0c to +70c temperature under bias ..........C10c to +80c extended operating temperature during read/erase/program ....C40c to +85c temperature under bias ..........C40c to +85c storage temperature....................C65c to +125c voltage on any pin (except v cc , v pp , a 9 and rp#) with respect to gnd..............C2.0v to +7.0v (2) voltage on pin rp# or pin a 9 with respect to gnd......... C2.0v to +13.5v (2,3) v pp program voltage with respect to gnd during block erase and word/byte program .... C2.0v to +14.0v (2,3) v cc supply voltage with respect to gnd..............C2.0v to +7.0v (2) output short circuit current ................... 100 ma (4) notice: this document contains information on products in the design phase of development. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. 1. operating temperature is for commercial product defined by this specification. 2. minimum dc voltage is C0.5v on input/output pins. during transitions, this level may undershoot to C2.0v for periods <20 ns. maximum dc voltage on input/output pins is v cc + 0.5v which, during transitions, may overshoot to v cc + 2.0v for periods <20 ns. 3. maximum dc voltage on v pp may overshoot to +14.0v for periods <20 ns. maximum dc voltage on rp# or a 9 may overshoot to 13.5v for periods <20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 5.2 test conditions test points input output 1.5 3.0 0.0 1.5 0599-10 figure 10. high speed test waveform note: ac test inputs are driven at 3.0v for a logic 1 and 0.0v for a logic 0. input timing begins, and output timing ends, at 1.5v. input rise and fall times (10% to 90%) <10 ns. test points input output 2.0 0.8 0.8 2.0 2.4 0.45 0599-11 figure 11. standard test waveform note: ac test inputs driven at v oh (2.4 v ttl ) for logic 1 and v ol (0.45 v ttl ) for logic 0. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ) . output timing ends at v ih and v il . input rise and fall times (10% to 90%) <10 ns. c l out v cc device under test r 1 r 2 0599-12 note: c l includes jig capacitance. figure 12. test configuration test configuration component values test configuration c l (pf) r 1 ( w )r 2 ( w ) 5v standard test 100 580 390 5v high-speed test 30 580 390
e smart 5 boot block memory family 27 product preview 5.3 operating conditions table 10. temperature and v cc operating conditions symbol parameter notes min max units t a commercial operating temperature 0 +70 c extended operating temperature -40 +85 c v cc 5v v cc supply voltage (10%) 1 4.50 5.50 volts 5v v cc supply voltage (5%) 2 4.75 5.25 volts v pp 5v v pp supply voltage (10%) 1 4.50 5.50 volts 12v v cc supply voltage (5%) 1 11.4 12.6 volts notes: 1. 10% v cc specifications apply to the standard test configuration (figures 11 and 12). 2. 5% v cc specifications apply to the high-speed test configuration (figures 10 and 12). 5.4 reset operations ih v il v rp# (p) plph t ih v il v rp# (p) plph t (a) reset during read mode abort complete phqv t phwl t phel t phqv t phwl t phel t (b) reset during program or block erase, < plph t plrh t plrh t ih v il v rp# (p) plph t abort complete phqv t phwl t phel t plrh t deep power- down (c) reset program or block erase, > plph t plrh t 0599-13 figure 13. ac waveform for reset operation table 11. reset specifications (1) sym parameter min max unit t plph rp# pulse low time 60 ns t plrh rp# low to reset during prog/erase 12 m s 1. if rp# is tied to v cc , these specs are not applicable. 2. these specifications are valid for all product versions (packages and speeds). 3. if rp# is asserted while a program or block erase, is not executing, the reset will complete within t plph . 4. a reset time, t phqv , is required after t plrh until outputs are valid. see section 3.1.5 for detailed information.
smart 5 boot block memory family e 28 product preview 5.6 electrical specifications table 12. dc characteristics (commercial and extended temperature) temp comm extended sym parameter note typ max typ max unit test condition i il input load current 1 1.0 1.0 a v cc = v cc max, v in = v cc or gnd i lo output leakage current 1 10 10 a v cc = v cc max, v in = v cc or gnd i ccs v cc standby current 1,3 2.0 2.5 ma v cc = v cc max, ce# = rp# = byte# = wp# = v ih 130 150 a v cc = v cc max ce# = rp# = v cc 0.2v i ccd v cc deep power-down current 188av cc = v cc max, v in = v cc or gnd rp# = gnd 0.2v i ccr v cc read current (word or byte mode) 1,5, 6 60 65 ma cmos inputs v cc = v cc max, ce# = gnd, oe# = v cc, f = 10 mhz (5v), i out = 0 ma, inputs=gnd or v cc 65 70 ma ttl inputs v cc = v cc max, ce# = v il , oe# = v ih , f = 10 mhz (5v), i out = 0 ma, inputs = v il or v ih i ccw v cc program current 1,4 50 50 ma v pp = v pph 1 (at 5v) (word or byte mode) 45 45 ma v pp = v pph 2 (at 12v) i cce v cc erase current 1,4 35 45 ma v pp = v pph 1 (at 5v) 30 40 ma v pp = v pph 2 (at 12v) i cces v cc erase susp current 1,2 10 12.0 ma ce# = v ih , block erase suspend i pps v pp standby current 1 10 15 a v pp < v pph 2 i ppd v pp deep power-down current 1 5.0 10 a rp# = gnd 0.2v i ppr v pp read current 1 200 200 a v pp 3 v pph 2 i ppw v pp program current 1,4 25 30 ma v pp = v pph 1 (at 5v) (word or byte mode) 20 25 v pp = v pph 2 (at 12v) i ppe v pp erase current 1,4 20 25 ma v pp = v pph 1 (at 5v) 15 20 v pp = v pph 2 (at 12v) i ppes v pp erase susp current 1 200 200 a v pp = v pph , block erase suspend i rp# rp# unlock current 1,4 500 500 a rp# = v hh (to unlock boot block) i id a 9 identifier current 1,4 500 500 a a 9 = v id
e smart 5 boot block memory family 29 product preview table 12. dc characteristics (commercial and extended temperature) (continued) temp comm/ext sym parameter note min max unit test condition v id a 9 intelligent identifier voltage 11.4 12.6 v v il input low voltage C0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5v v v ol output low voltage 0.45 v v cc = v cc min, i ol = 5.8 ma v oh 1 output high voltage (ttl) 2.4 v v cc = v cc min, i oh = C2.5 ma v oh 2 output high voltage (cmos) 0.85 x v cc vv cc = v cc min, i oh = C2.5 ma v cc C 0.4v vv cc = v cc min, i oh = C100 m a v pplk v pp lock-out voltage 3 0.0 1.5 v complete data protection v pph 1v pp (prog/erase operations) 4.5 5.5 v v pp at 5v v pph 2v pp (prog/erase operations) 11.4 12.6 v v pp at 12v v lko v cc erase/prog lock voltage 2.0 v v hh rp# unlock voltage 11.4 12.6 v boot block program/erase notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0v, t = +25c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device deselected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases and word/byte program operations are inhibited when v pp = v pplk , and not guaranteed in the range between v pph 1 and v pplk . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to less than 1 ma typical, in static operation. 6. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . table 13. capacitance (t a = 25 c, f = 1 mhz) symbol parameter note typ max unit conditions c in input capacitance 4 6 8 pf v in = 0v c out output capacitance 4, 7 10 12 pf v out = 0v 1. sampled, not 100% tested.
smart 5 boot block memory family e 30 product preview table 14. ac characteristics: read operations (commercial and extended temperature) temp commercial extended speed -60/-70 -80/-90 -80/-90 # sym parameter v cc 5v 5% (4) 5v 10% (5) 5v 10% (5) 5v 10% (5) unit load 30 pf 100 pf 100 pf 100 pf notes min max min max min max min max r1 t avav read cycle 2-, 4-mbit 60 70 80 80 ns time 8-mbit 70 80 90 90 ns r2 t avqv address to 2-, 4-mbit 60 70 80 80 ns output delay 8-mbit 70 80 90 90 ns r3 t elqv ce# to 2-, 4-mbit 2 60 70 80 80 ns output delay 8-mbit 70 80 90 90 ns r4 t glqv oe# to output delay 2 30 35 40 40 ns r5 t phqv rp# to output delay 450 450 450 450 ns r6 t elqx ce# to output in low z 3 0 0 0 0 ns r7 t glqx oe# to output in low z 3 0 0 0 0 ns r8 t ehqz ce# to output in high z 3 20 20 20 25 ns r9 t ghqz oe# to output in high z 3 20 20 20 25 ns r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 30 0 0 0 ns notes: 1. see ac input/output reference waveform for timing measurements. 2. oe# may be delayed up to t ce Ct oe after the falling edge of ce# without impact on t ce . 3. sampled, but not 100% tested. 4. see test configurations (figure 12), 5v high-speed test component values. 5. see test configurations (figure 12), 5v standard test component values. 6. dynamic byte# switching between word and byte modes is not supported. mode changes must be made when the device is in deep power-down or powered down.
e smart 5 boot block memory family 31 product preview address stable device and address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# (e) oe# (g) we# (w) data (d/q) ih v il v rp#(p) ol v oh v high z valid output data valid standby high z r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 0599-14 figure 14. ac waveforms for read operations
smart 5 boot block memory family e 32 product preview table 15. ac characteristics: write operations (commercial and extended temperature) comm extended # sym parameter note min max min max unit w1 t phwl (t phel ) rp# high recovery to we# (ce#) going low 450 450 ns w2 t elwl (t wlel ) ce# (we#) setup to we# (ce#) going low 00ns w3 t wp write pulse width 9 50 60 ns w4 t dvwh (t dveh ) data setup to we# (ce#) going high 4 50 60 ns w5 t avwh (t aveh ) address setup to we# (ce#) going high 3 50 60 ns w6 t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 0 ns w7 t whdx (t ehdx ) data hold from we# (ce#) high 4 0 0 ns w8 t whax (t ehax ) address hold from we# (ce#) high 3 0 0 ns w9 t wph write pulse width high v cc = 5v 5% 10 10 ns v cc = 5v 10% 20 20 ns w10 t phhwh (t phheh ) rp# v hh setup to we# (ce#) going high 6,8 100 100 ns w11 t vpwh (t vpeh )v pp setup to we# (ce#) going high 5,8 100 100 ns w12 t qvph rp# v hh hold from valid srd 6,8 0 0 ns w13 t qvvl v pp hold from valid srd 5,8 0 0 ns w14 t phbr boot block lock delay 7,8 100 100 ns notes: 1. read timing characteristics during program and erase operations are the same as during read-only operations. refer to ac characteristics for read operations. 2. the on-chip wsm completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify operations. 3. refer to command definition table for valid a in . (table 7) 4. refer to command definition table for valid d in . (table 7) 5. program/erase durations are measured to valid srd data (successful operation, sr.7 = 1). 6. for boot block program/erase, rp# should be held at v hh or wp# should be held at v ih until operation completes successfully. 7. time t phbr is required for successful locking of the boot block. 8. sampled, but not 100% tested. 9. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . 10. write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low first). hence, t wph = t whwl = t ehel = t whel = t ehwl .
e smart 5 boot block memory family 33 product preview addresses [a] ce#(we#) [e(w)] oe# [g] we#(ce#) [w(e)] data [d/q] rp# [p] ih v il v ih v il v ih v il v ih v il v hh v 6.5v il v il v in d in a in a valid srd in d ih v high z ih v il v v [v] pp pph v pplk v pph v1 2 wp# il v ih v in d ab c d e f w8 w6 w9 w3 w4 w7 w1 w5 w2 w10 w12 w11 w13 0599-15 note: a. v cc power-up and standby. b. write program setup or erase setup command. c. write valid address & data (if program operation) or erase confirm (if erase operation) command. d. automated program or erase delay. e. read status register data. f. write read array command if write operations are completed. figure 15. ac waveforms for write operations
smart 5 boot block memory family e 34 product preview table 16. erase and program timings, v cc = 5v 10% (commercial and extended temperature) temp commercial extended v pp 5v 10% 12v 5% 5v 10% 12v 5% parameter typ max typ max typ max typ max units boot/parameter block erase time 7 7 7 7 s main block erase time 14 14 14 14 s main block write time (byte mode) s main block write time (word mode) s byte program time 100 100 100 100 m s word program time 100 100 100 100 m s notes: 1. all numbers are sampled, not 100% tested. 2. max erase times are specified under worst case conditions. the max erase times are tested at the same value independent of v cc and v pp . see note 3 for typical conditions. 3. typical conditions are 25c with v cc and v pp at the center of the specified voltage range. production programming using v cc = 5.0v, v pp = 12.0v typically results in a 60% reduction in programming time. 4. contact your intel representative for information regarding maximum byte/word write specifications. 5. max program times are guaranteed for the two parameter blocks and 96-kb main block only.
e smart 5 boot block memory family 35 product preview appendix a ordering information product line designator for all intel flash products density / organization x00 = x8/x16 selectable (x = 2, 4, 8) access speed , ns architecture b = boot block operating temperature t = extended temp blank = commercial temp package e = tsop pa = 44-lead psop tb = ext. temp 44-lead psop e28f4 0 0 b5 - t 0 6 t = top boot b = bottom boot voltage options (v / v ) 5 = (5 or 12 / 5) pp cc 0599_16 valid combinations 44-lead psop 48-lead tsop commercial 2m pa28f200b5t60 e28f200b5t60 pa28f200b5b60 e28f200b5b60 pa28f200b5t80 e28f200b5t80 pa28f200b5b80 e28f200b5b80 4m pa28f400b5t60 e28f400b5t60 pa28f400b5b60 e28f400b5b60 pa28f400b5t80 e28f400b5t80 pa28f400b5b80 e28f400b5b80 8m pa28F800B5t70 e28F800B5t70 pa28F800B5b70 e28F800B5b70 pa28F800B5t90 e28F800B5t90 pa28F800B5b90 e28F800B5b90 extended 2m tb28f200b5t80 te28f200b5t80 tb28f200b5b80 te28f200b5b80 4m tb28f400b5t80 te28f400b5t80 tb28f400b5b80 te28f400b5b80 8m tb28F800B5t90 te28F800B5t90 tb28F800B5b90 te28F800B5b90
smart 5 boot block memory family e 36 product preview appendix b write state machine: current-next state chart write state machine current/next states command input (and next state) current state sr.7 data when read read array (ffh) program setup (10/40h) erase setup (20h) erase confirm (d0h) erase susp. (b0h) erase resume (d0h) read status (70h) clear status (50h) read id (90h) read array 1 array read array program setup erase setup read array read status read array read id program setup 1 status program (command input = data to be programmed) program: not complete 0 status program program: complete 1 status read array program setup erase setup read array read status read array read id erase setup 1 status erase command error erase erase cmd. error erase erase command error erase cmd. error 1 status read array program setup erase setup read array read status read array read id erase: not complete 0 status erase erase susp. to status erase erase: complete 1 status read array program setup erase setup read array read status read array read id erase suspend to status 1 status erase susp. to array resd. erase susp. to array erase erase susp. to array erase erase susp. to status erase susp. to array resd. erase suspend to array 1 array erase susp. to array resd. erase susp. to array erase erase susp. to array erase erase susp. to status erase susp. to array resd. read status 1 status read array program setup erase setup read array read status read array read id read identifier 1 id read array program setup erase setup read array read status read array read id
e smart 5 boot block memory family 37 product preview appendix c product block diagram 7769_01
smart 5 boot block memory family e 38 product preview appendix d additional information order number document 292194 ab-65 migrating smartvoltage boot block flash designs to smart 5 flash 292154 ab-60 smartvoltage boot block flash memory family overview 290531 2-mbit smartvoltage boot block flash memory family datasheet 290530 4-mbit smartvoltage boot block flash memory family datasheet 290539 8-mbit smartvoltage boot block flash memory family datasheet 290448 28f002/200bx-t/b 2-mbit boot block flash memory datasheet 290449 28f002/200bl-t/b 2-mbit low power boot block flash memory datasheet 290450 28f002/400bl-t/b 4-mbit low power boot block flash memory datasheet 290451 28f002/400bx-t/b 4-mbit boot block flash memory datasheet

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